1. Field of the Invention
The present invention relates to a substrate voltage applying circuit for a semiconductor device, and more particularly, to a substrate voltage applying circuit that selectively generates a substrate voltage.
2. Background of the Related Art
A conventional CMOS twin-well process applied to semiconductor devices includes a P-well and an N-well that respectively receive a substrate voltage Vbb and a power source voltage Vcc. However, as the semiconductor devices become increasingly integrated, a related art triple-well process has been introduced to miniaturize the semiconductor devices and to improve reliability.
As shown in FIG. 1, in the related art triple-well process the semiconductor device includes a memory cell unit 1 having a P-well surrounded by a deep N-well and a peripheral circuit unit 2 provided with a P-well and an N-well. A ground voltage Vss and a power source voltage Vcc are supplied to the P-well and the N-well, respectively, of the peripheral circuit unit 2. The power source voltage Vcc (not shown) or a boost voltage Vpp, and a substrate voltage Vbb are supplied to the deep N-well and the P-well, respectively, of the memory cell unit 1. A related art substrate voltage applying circuit in the semiconductor device supplies the substrate voltage Vbb to the P-well of the memory cell unit 1.
FIG. 2 is a block diagram showing the related art substrate voltage applying circuit that includes an oscillation circuit 10 for generating an oscillation signal OSC and a pumping unit 20 for carrying out a voltage pumping operation in accordance with the oscillation signal OSC from the oscillation circuit 10 to generate the substrate voltage Vbb. A level sensing unit 30 senses a level of the substrate voltage Vbb outputted from the pumping unit 20 in accordance with a predetermined set sensing point and generates a sensing signal OSCSW.
The oscillation circuit 10 and the pumping unit 20 can employ conventional devices. Accordingly, a detailed description is omitted.
The level sensing unit 30 includes a sensing NMOS transistor N1 with a source and a substrate that receive the substrate voltage Vbb from the pumping unit 20. A gate of the sensing NMOS transistor N1 receives the ground voltage Vss and a drain is connected to the oscillation circuit 10. The sensing NMOS transistor N1 is located in the deep N-well of the memory cell unit 1 in FIG. 1.
With reference to FIG. 2, operation of the related art substrate voltage applying circuit will now be described. The pumping unit 20 performs the pumping operation in accordance with the oscillation signal OSC from the oscillation circuit 10 and supplies the substrate voltage Vbb to the memory cell unit 1. When the substrate voltage Vbb from the pumping unit 20 that is sensed by the level sensing unit 30 becomes a predetermined level, which is the sensing point, the level sensing unit 30 generates the sensing signal OSCSW to suspend the oscillation circuit 10. When the substrate voltage Vbb is under the predetermined level, the level sensing unit 30 outputs the sensing signal OSCSW to continuously drive the oscillation circuit 10. The sensing point is a predetermined level.
As shown in FIG. 3, when a level A of the substrate voltage Vbb from the pumping unit 20 is lower than the predetermined voltage level that is the sensing point, the sensing NMOS transistor N1 of the level sensing unit 30 is turned off. Thus, the oscillation circuit 10 is suspended. When a level B of the substrate voltage Vbb is higher than the predetermined voltage level, the sensing NMOS transistor N1 is turned on and outputs the substrate voltage Vbb. Accordingly, the oscillation circuit 10 is again operated. Here, the sensing point or the predetermined voltage level of the level sensing unit 30 is determined by the turn-on voltage of the sensing NMOS transistor N1.
The operation of the oscillation circuit 10 is controlled in accordance with the sensing signal OSCSW outputted from the level sensing unit 30. Thus, the substrate voltage applying circuit supplies the constant substrate voltage Vbb to the memory cell unit 1.
The memory cell of the related art semiconductor device has the P-well that is in the deep N-well. Thus, in a level test of a wafer, the substrate voltage applying circuit is suspended, and a power source at a desirable level is externally applied to an substrate voltage input pad.
However, as described above, the related art triple well memory cell and peripheral circuit and the related art substance voltage applying circuit have various disadvantages. Externally changing and supplying the substrate voltage when a semiconductor package is completely fabricated is difficult or impossible. Further, evaluation according to the substrate voltage is difficult or can not be achieved in the case of analyzing inferior memory cells and determining properties of memory cells.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.